/*
 * Allwinner SoCs hdmi2.0 driver.
 *
 * Copyright (C) 2016 Allwinner.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef INCLUDE_IDENTIFICATION_IDENTIFICATION_H_
#define INCLUDE_IDENTIFICATION_IDENTIFICATION_H_

#include "hdmitx_dev.h"
#include "log.h"
#include "access.h"

#define PRODUCT_HDMI_TX  0xA0

/*****************************************************************************
 *                                                                           *
 *                          Identification Registers                         *
 *                                                                           *
 *****************************************************************************/

/* Design Identification Register */
#define DESIGN_ID  0x00000000
#define DESIGN_ID_DESIGN_ID_MASK  0x000000FF /* Design ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller */

/* Revision Identification Register */
#define REVISION_ID  0x00000004
#define REVISION_ID_REVISION_ID_MASK  0x000000FF /* Revision ID code fixed by Synopsys that Identifies the instantiated DWC_hdmi_tx controller */

/* Product Identification Register 0 */
#define PRODUCT_ID0  0x00000008
#define PRODUCT_ID0_PRODUCT_ID0_MASK  0x000000FF /* This one byte fixed code Identifies Synopsys's product line ("A0h" for DWC_hdmi_tx products) */

/* Product Identification Register 1 */
#define PRODUCT_ID1  0x0000000C
#define PRODUCT_ID1_PRODUCT_ID1_TX_MASK  0x00000001 /* This bit Identifies Synopsys's DWC_hdmi_tx Controller according to Synopsys product line */
#define PRODUCT_ID1_PRODUCT_ID1_RX_MASK  0x00000002 /* This bit Identifies Synopsys's DWC_hdmi_rx Controller according to Synopsys product line */
#define PRODUCT_ID1_PRODUCT_ID1_HDCP_MASK  0x000000C0 /* These bits identify a Synopsys's HDMI Controller with HDCP encryption according to Synopsys product line */

/* Configuration Identification Register 0 */
#define CONFIG0_ID  0x00000010
#define CONFIG0_ID_HDCP_MASK  0x00000001 /* Indicates if HDCP is present */
#define CONFIG0_ID_CEC_MASK  0x00000002 /* Indicates if CEC is present */
#define CONFIG0_ID_CSC_MASK  0x00000004 /* Indicates if Color Space Conversion block is present */
#define CONFIG0_ID_HDMI14_MASK  0x00000008 /* Indicates if HDMI 1 */
#define CONFIG0_ID_AUDI2S_MASK  0x00000010 /* Indicates if I2S interface is present */
#define CONFIG0_ID_AUDSPDIF_MASK  0x00000020 /* Indicates if the SPDIF audio interface is present */
#define CONFIG0_ID_PREPEN_MASK  0x00000080 /* Indicates if it is possible to use internal pixel repetition */

/* Configuration Identification Register 1 */
#define CONFIG1_ID  0x00000014
#define CONFIG1_ID_CONFAPB_MASK  0x00000002 /* Indicates that configuration interface is APB interface */
#define CONFIG1_ID_HDMI20_MASK  0x00000020 /* Indicates if HDMI 2 */
#define CONFIG1_ID_HDCP22_MASK  0x00000040 /* Indicates if HDCP 2 */

/* Configuration Identification Register 2 */
#define CONFIG2_ID  0x00000018
#define CONFIG2_ID_PHYTYPE_MASK  0x000000FF /* Indicates the type of PHY interface selected: 0x00: Legacy PHY (HDMI TX PHY) 0xF2: PHY GEN2 (HDMI 3D TX PHY) 0xE2: PHY GEN2 (HDMI 3D TX PHY) + HEAC PHY 0xC2: PHY MHL COMBO (MHL+HDMI 2 */

/* Configuration Identification Register 3 */
#define CONFIG3_ID  0x0000001C
#define CONFIG3_ID_CONFGPAUD_MASK  0x00000001 /* Indicates that the audio interface is Generic Parallel Audio (GPAUD) */
#define CONFIG3_ID_CONFAHBAUDDMA_MASK  0x00000002 /* Indicates that the audio interface is AHB AUD DMA */


/**
 * Read product design information
 * @param baseAddr base address of controller
 * @return the design number stored in the hardware
 */
u8 id_design(hdmi_tx_dev_t *dev);

/**
 * Read product revision information
 * @param baseAddr base address of controller
 * @return the revision number stored in the hardware
 */
u8 id_revision(hdmi_tx_dev_t *dev);

/**
 * Read product line information
 * @param baseAddr base address of controller
 * @return the product line stored in the hardware
 */
u8 id_product_line(hdmi_tx_dev_t *dev);

/**
 * Read product type information
 * @param baseAddr base address of controller
 * @return the product type stored in the hardware
 */
u8 id_product_type(hdmi_tx_dev_t *dev);

/**
 * Check if HDCP is instantiated in hardware
 * @param baseAddr base address of controller
 * @return TRUE if hardware supports HDCP encryption
 */
int id_hdcp_support(hdmi_tx_dev_t *dev);

int id_hdcp14_support(hdmi_tx_dev_t *dev);

int id_hdcp22_support(hdmi_tx_dev_t *dev);

int id_phy(hdmi_tx_dev_t *dev);

#endif /* INCLUDE_IDENTIFICATION_IDENTIFICATION_H_ */


